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Super symbol-computing Archives

Kanada, Y., 26th Programming Symposium, pp. 47-56, 1985.


[ 日本語のページ ]
[ Paper PDF file (in Japanese, 2 MB) ]
[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Explanation: There are many research results on high-speed execution of Prolog (logic programming language) by using parallel or pipelined scalar computers. However, this paper aimed accelerating logic language execution by using so-called supercomputer, i. e., vector-type pipelined computers at the first time. This paper only showed the outline of the method, but the following research enabled acceleration for a cirtain range of programs.

Keywords: Logic programming language, Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Kanada, Y., SIG on Programming Language, IPSJ, PL-87-12, 1987.

[ 日本語のページ ]
[ No English abstract is available. ]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Logic programming language, Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Torii, S., Kojima, K., Kanada, Y., Sakata, A., Yoshizumi, S., and Takahashi, M., 4th Int'l Conf. on Data Engineering, pp. 194-201, 1988.

[ 日本語のページ ]
[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Non-numerical processing, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Kanada, Y., Kojima, K., and Sugaya, M., ACM International Conference on Supercomputing, pp. 539-549, St. Malo, 1988.

[ 日本語のページ ]
[ Paper PDF file ]

Abstract: Several techniques for running Prolog programs on pipelined vector processors, such as the Hitachi S-820 or the Cray-2, are developed. This paper presents an automatic program transformation (vectorization) method of Prolog, which enables a type of or-parallel execution of Prolog programs using vector operations. Performance is evaluated on the Hitachi S-810 using the Eight-Queens Problem. Its vector execution speed is 4.5 MLIPS (18 ms). This is eight or nine times faster than scalar execution. This result confirms the effectiveness of vectorization techniques and applicability of vector prodcessors to Prolog execution and symbol processing applications.

[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Logic programming language, Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Kanada, Y., Kojima, K., and Sugaya, M., Journal of Information Processing Society of Japan, Vol. 29, No. 10, pp. 985-994, 1988.

[ 日本語のページ ]
[No English abstract is available.]
[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Search problem, Combinatorial problem, Backtrack, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Kanada, Y., and Sugaya, M., Journal of Information Processing Society of Japan, Vol. 30, No. 4, pp. 495-506, 1989.

[ 日本語のページ ]
[No English abstract is available.]
[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Logic programming language, Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Kanada, Y., and Sugaya, M., International Joint Conference on Artificial Intelligence '89, pp. 151-156, 1989.

[ 日本語のページ ]
[ Paper PDF file]

Abstract: This paper describes a technique for executing logic programming languages such as Prolog for the Cray-type vector processors. This technique, which we call the parallel backtracking technique, enables a kind of or-parallel execution without process explosion. The compiled intermediate language code for the parallel backtracking execution is the same as the code presented in our previous paper. The compilation is based on a kind of program transformation called or-vectorization. However, the interpretation of the intermediate code is changed to enable the parallel backtracking execution. An execution simulator and a compiler prototype were developed. We have not yet implemented this technique to our native code execution system, but we expect a performance of eight times or more higher than scalar processing upon implementation.

[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Logic programming language, Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Kanada, Y., and Sugaya, M., Journal of Information Processing Society of Japan, Vol. 30, No. 7, 856-868, 1989.

[ 日本語のページ ]
[ No English abstract is available. ]
[ No English abstract is available. ]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Program transformation, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing, Programming language processor, N queens problem

Kanada, Y., PARBASE-90, IEEE, pp. 147-151, 1990.

[ 日本語のページ ]
[ Paper PDF file ]
[ Paper postscript file ]
[ IEEExplore Paper page ]

Abstract: This paper presents a vectorized algorithm for entering data into a hash table. A program that enters multiple data could not be executed on vector processors by conventional vectorization techniques because of data dependences. Our method enables execution of multiple data entry by conventional vector processors and improves the performance by a factor of 12.7 when entering 4099 pieces of data on the Hitachi S-810, compared to the normal sequential method. This method is applied to the address calculation sorting and the distribution counting sort, whose main part was unvectorizable by previous techniques. It improves performance by a factor of 12.8 when n = 2^14 on the S-810.

[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Sorting, Hashing, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Kanada, Y., and Sugaya, M., 41th National Conference of IPSJ, 1990.

[ 日本語のページ ]
[No English abstract is available.]
[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Logic programming language, Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Kanada, Y., and Sugaya, M., 42th IPSJ National Conference, 4M-2, 1991.

[ 日本語のページ ]
[No English abstract is available.]
[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Logic programming language, Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing, Shared data vector processing

Kanada, Y., International Conference on Supercomputing '91, Albuquerque, 1991.

[ 日本語のページ ]
[ Paper PDF file (ACM DL) ]
[ Paper PDF file (invalid characters contained)] [ Paper postscript file ]
[ This is an older version of paper 13.. ]
[ IEEExplore Paper page ]

Abstract: The conventional processing techniques for pipelined vector processors such as Cray-XMP, or SIMD parallel processors, such as CM-2 (connection machine), are generally applied only to independent multiple data processing. This paper describes a vector processing method of multiple processings including parallel rewriting of dynamic data structures with shared elements, and of multiple processings that may rewrite the same data element two or more times. This method is called the filtering-overwritten-label method (FOL). FOL enables vector processing of entering multiple data into a hash table, address calculation sorting, and many other algorithms that handle lists, trees, graphs and other types of symbolic data structures. FOL is applied to several symbolic processing algorithms; consequently, the performance is improved by a factor of ten on the Hitachi S-810.

[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing, Shared data vector processing

Kanada, Y., and Sugaya, M., 8th Annual Conference of Software Science Society, 1991.

[ 日本語のページ ]
[ No English abstract is available. ]
[ No English abstract is available. ]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing, Multi vector

Kanada, Y., Ph.D Thesis, University of Tokyo Graduate School, 1992.

[ 日本語のページ ]
[ Kindle edition: Vector-processing Methods of Symbol-processing Programs and Its Application to Logic Language Programs ]
[ Contents of PDF Version Paper (Japanese) ]

I developed vector processing methods of symbol-processing programs and automatic vectorization methods of logic language programs (execution on Cray-1 type computers).
-- I believe you can get some knowledge from this paper when thinking of automatic parallelization for SIMD computers.

[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Logic programming language, Programming language processor, Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Kanada, Y., Parallel Computing, Vol. 19, 1993, pp. 1155-1175.

[ 日本語のページ ]
[ Paper PDF file (invalid characters contained)]
[ Paper postscript file ]

Abstract: Conventional processing techniques for pipelined vector processors such as the Cray-XMP, or data-parallel computers, such as the Connection Machines, are generally applied only to independent multiple data prcessing. This paper describes a vector processing method for multiple processings including parallel rewriting of dynamic data strutures with shared elements, and for mutiple procesings that may rewrite the same data item multiple times. This method enables vector processing when entering mutiple data items into a hash table, address calculation sorting, and many other algorithms that handle lists, trees, graphs and other types of symbolic data structures. This method is aplied to several algorithms; consequently, the peformance is improved by a fator of ten on a Hitachi S-810.

[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Vectorization of symbol processing, Vectorized symbol processing, Parallel symbol processing, Supercomputing, Super symbol processing, Parallel processing, Vector processing

Torii, S., Kojima, K., Kanada, Y., Sakata, A., Takahashl, M., Journal of Information Processing, Vol. 34, No. 1, pp. 109-119, 1993-1.

[ 日本語のページ ]
[ PDF paper entry (IPSJ) ]
[No English abstract is available.]
[No English abstract is available.]

Introduction to this research theme: Logic/Symbolic Vector Processing

Keywords: Vector processing, Vectorization, Merge operation, Relational database, Integrated Database Processor, IDP, Non-numerical processing, Sorting, N queens problem